// +FHDR----------------------------------------------------------
// Copyright (c) 2023, RJMicro Technology Co.,Ltd.
// RJMicro Confidential Proprietary
// ---------------------------------------------------------------
// FILE NAME       : .v
// DEPARTMENT      : IC Dept
// AUTHOR          :
// AUTHOR'S EMAIL  :
// ---------------------------------------------------------------
//
// Description     :
// 12'h000  CHIPID
// 12'h020  RDP
// 12'h100  RAM0IER
// 12'h104  RAM0ISR
// 12'h108  RAM0ICLR
// 12'h110  RAM0SYND
// 12'h114  RAM0INJL
// 12'h118  RAM0INJH
// 12'h130  RAM1IER
// 12'h134  RAM1ISR
// 12'h138  RAM1ICLR
// 12'h140  RAM1SYND
// 12'h144  RAM1INJL
// 12'h148  RAM1INJH
// 12'h200  ADC0TRG
// 12'h204  ADC1TRG
// 12'h208  TIM0TRG
// 12'h20C  TIM1TRG
// 12'h210  TIM2TRG
// 12'h214  TRGO0
// 12'h218  TRGO1
// 12'hE00  DBGEN
// 12'hE04  DBGLOCK
// 12'hE08  DBGMODE
// 12'hF00  DFTEN
// 12'hF04  DFTLOCK
// 12'hF08  DFTMODE
// 12'hF10  OSCHENR
// 12'hF14  OSCHENLOCKR
// 12'h300  REMAPR
// -FHDR
// ---------------------------------------------------------------

module syscfg_regfile (
    output [31:0]          chipid              ,
    output                 rdp                 ,
    output                 ram0ier_en          ,
    input  [01:0]          ram0isr_err         ,
    output           ram0iclr_errclr     ,
    input  [06:0]          ram0synd_synd       ,
    output [31:0]          ram0injl_injl       ,
    output [06:0]          ram0injh_injh       ,
    output                 ram1ier_en          ,
    input  [01:0]          ram1isr_err         ,
    output           ram1iclr_errclr     ,
    input  [06:0]          ram1synd_synd       ,
    output [31:0]          ram1injl_injl       ,
    output [06:0]          ram1injh_injh       ,
    output                 adc0trg_epwm_cmp0   ,
    output                 adc0trg_epwm_cmp1   ,
    output                 adc0trg_epwm_cmp2   ,
    output                 adc0trg_epwm_cmp3   ,
    output                 adc0trg_epwm_cmp4   ,
    output                 adc0trg_epwm_cmp5   ,
    output                 adc0trg_epwm_trgo   ,
    output                 adc0trg_epwm_oc0    ,
    output                 adc0trg_epwm_oc1    ,
    output                 adc0trg_epwm_oc2    ,
    output                 adc0trg_epwm_oc3    ,
    output                 adc0trg_tim0_up     ,
    output                 adc0trg_tim1_up     ,
    output                 adc0trg_tim2_up     ,
    output                 adc0trg_ediag_cmp   ,
    output                 adc1trg_epwm_cmp0   ,
    output                 adc1trg_epwm_cmp1   ,
    output                 adc1trg_epwm_cmp2   ,
    output                 adc1trg_epwm_cmp3   ,
    output                 adc1trg_epwm_cmp4   ,
    output                 adc1trg_epwm_cmp5   ,
    output                 adc1trg_epwm_trgo   ,
    output                 adc1trg_epwm_oc0    ,
    output                 adc1trg_epwm_oc1    ,
    output                 adc1trg_epwm_oc2    ,
    output                 adc1trg_epwm_oc3    ,
    output                 adc1trg_tim0_up     ,
    output                 adc1trg_tim1_up     ,
    output                 adc1trg_tim2_up     ,
    output                 adc1trg_ediag_cmp   ,
    output                 tim0trg_epwm_cmp0   ,
    output                 tim0trg_epwm_cmp1   ,
    output                 tim0trg_epwm_cmp2   ,
    output                 tim0trg_epwm_cmp3   ,
    output                 tim0trg_epwm_cmp4   ,
    output                 tim0trg_epwm_cmp5   ,
    output                 tim0trg_epwm_trgo   ,
    output                 tim0trg_epwm_oc0    ,
    output                 tim0trg_epwm_oc1    ,
    output                 tim0trg_epwm_oc2    ,
    output                 tim0trg_epwm_oc3    ,
    output                 tim0trg_tim0_up     ,
    output                 tim0trg_tim1_up     ,
    output                 tim0trg_tim2_up     ,
    output                 tim0trg_ediag_cmp   ,
    output                 tim1trg_epwm_cmp0   ,
    output                 tim1trg_epwm_cmp1   ,
    output                 tim1trg_epwm_cmp2   ,
    output                 tim1trg_epwm_cmp3   ,
    output                 tim1trg_epwm_cmp4   ,
    output                 tim1trg_epwm_cmp5   ,
    output                 tim1trg_epwm_trgo   ,
    output                 tim1trg_epwm_oc0    ,
    output                 tim1trg_epwm_oc1    ,
    output                 tim1trg_epwm_oc2    ,
    output                 tim1trg_epwm_oc3    ,
    output                 tim1trg_tim0_up     ,
    output                 tim1trg_tim1_up     ,
    output                 tim1trg_tim2_up     ,
    output                 tim1trg_ediag_cmp   ,
    output                 tim2trg_epwm_cmp0   ,
    output                 tim2trg_epwm_cmp1   ,
    output                 tim2trg_epwm_cmp2   ,
    output                 tim2trg_epwm_cmp3   ,
    output                 tim2trg_epwm_cmp4   ,
    output                 tim2trg_epwm_cmp5   ,
    output                 tim2trg_epwm_trgo   ,
    output                 tim2trg_epwm_oc0    ,
    output                 tim2trg_epwm_oc1    ,
    output                 tim2trg_epwm_oc2    ,
    output                 tim2trg_epwm_oc3    ,
    output                 tim2trg_tim0_up     ,
    output                 tim2trg_tim1_up     ,
    output                 tim2trg_tim2_up     ,
    output                 tim2trg_ediag_cmp   ,
    output                 trgo0_epwm_cmp0     ,
    output                 trgo0_epwm_cmp1     ,
    output                 trgo0_epwm_cmp2     ,
    output                 trgo0_epwm_cmp3     ,
    output                 trgo0_epwm_cmp4     ,
    output                 trgo0_epwm_cmp5     ,
    output                 trgo0_epwm_trgo     ,
    output                 trgo0_epwm_oc0      ,
    output                 trgo0_epwm_oc1      ,
    output                 trgo0_epwm_oc2      ,
    output                 trgo0_epwm_oc3      ,
    output                 trgo0_tim0_up       ,
    output                 trgo0_tim1_up       ,
    output                 trgo0_tim2_up       ,
    output                 trgo0_ediag_cmp     ,
    output                 trgo1_epwm_cmp0     ,
    output                 trgo1_epwm_cmp1     ,
    output                 trgo1_epwm_cmp2     ,
    output                 trgo1_epwm_cmp3     ,
    output                 trgo1_epwm_cmp4     ,
    output                 trgo1_epwm_cmp5     ,
    output                 trgo1_epwm_trgo     ,
    output                 trgo1_epwm_oc0      ,
    output                 trgo1_epwm_oc1      ,
    output                 trgo1_epwm_oc2      ,
    output                 trgo1_epwm_oc3      ,
    output                 trgo1_tim0_up       ,
    output                 trgo1_tim1_up       ,
    output                 trgo1_tim2_up       ,
    output                 trgo1_ediag_cmp     ,
    output                 dbgen_en            ,
    output [07:0]          dbgen_key           ,
    output                 dbglock_lock        ,
    output [07:0]          dbglock_key         ,
    output [02:0]          dbgmode_mode        ,
    output                 dften_en            ,
    output [07:0]          dften_key           ,
    output                 dftlock_lock        ,
    output [07:0]          dftlock_key         ,
    output [03:0]          dftmode_mode        ,
    input                  hclk                ,
    input                  hrstn               ,

    input                  hready              ,
    input  [31:0]          haddr               ,
    input                  hwrite              ,
    input  [01:0]          htrans              ,
    input  [02:0]          hsize               ,
    input  [31:0]          hwdataa              ,

//   output                 hreadyout           ,
//   output                 hreadyout_peri      ,
    input                   hsel_syscfg         ,
    output [31:0]           hrdata_syscfg
);

// ------------------------------------------------------------
// AHB write read enable
// ------------------------------------------------------------
wire            ahb_cs    = hsel_syscfg & hready & htrans[1];
wire            read_en   = ahb_cs & (~hwrite);
reg     [11:2]  addr;
reg             write_en;
reg     [31:0]  ff_rdata;

always @(posedge hclk or negedge hrstn) begin
    if (~hrstn) begin
        addr      <= 6'h0;
        write_en  <= 1'h0;
    end else begin
        addr      <= haddr[11:2];
        write_en  <= ahb_cs & (~hwrite);
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        hrdata_syscfg <= 32'b0;
    else if (read_en) 
        hrdata_syscfg <= ff_rdata[31:0];
end

// ------------------------------------------------------------
// Internal Signals
// ------------------------------------------------------------
reg     [31:0]  ff_chipid           ;
reg             ff_rdp              ;
reg             ff_ram0ier_en       ;
reg       ff_ram0iclr_errclr  ;
reg     [31:0]  ff_ram0injl_injl    ;
reg     [06:0]  ff_ram0injh_injh    ;
reg             ff_ram1ier_en       ;
reg       ff_ram1iclr_errclr  ;
reg     [31:0]  ff_ram1injl_injl    ;
reg     [06:0]  ff_ram1injh_injh    ;
reg             ff_adc0trg_epwm_cmp0;
reg             ff_adc0trg_epwm_cmp1;
reg             ff_adc0trg_epwm_cmp2;
reg             ff_adc0trg_epwm_cmp3;
reg             ff_adc0trg_epwm_cmp4;
reg             ff_adc0trg_epwm_cmp5;
reg             ff_adc0trg_epwm_trgo;
reg             ff_adc0trg_epwm_oc0 ;
reg             ff_adc0trg_epwm_oc1 ;
reg             ff_adc0trg_epwm_oc2 ;
reg             ff_adc0trg_epwm_oc3 ;
reg             ff_adc0trg_tim0_up  ;
reg             ff_adc0trg_tim1_up  ;
reg             ff_adc0trg_tim2_up  ;
reg             ff_adc0trg_ediag_cmp;
reg             ff_adc1trg_epwm_cmp0;
reg             ff_adc1trg_epwm_cmp1;
reg             ff_adc1trg_epwm_cmp2;
reg             ff_adc1trg_epwm_cmp3;
reg             ff_adc1trg_epwm_cmp4;
reg             ff_adc1trg_epwm_cmp5;
reg             ff_adc1trg_epwm_trgo;
reg             ff_adc1trg_epwm_oc0 ;
reg             ff_adc1trg_epwm_oc1 ;
reg             ff_adc1trg_epwm_oc2 ;
reg             ff_adc1trg_epwm_oc3 ;
reg             ff_adc1trg_tim0_up  ;
reg             ff_adc1trg_tim1_up  ;
reg             ff_adc1trg_tim2_up  ;
reg             ff_adc1trg_ediag_cmp;
reg             ff_tim0trg_epwm_cmp0;
reg             ff_tim0trg_epwm_cmp1;
reg             ff_tim0trg_epwm_cmp2;
reg             ff_tim0trg_epwm_cmp3;
reg             ff_tim0trg_epwm_cmp4;
reg             ff_tim0trg_epwm_cmp5;
reg             ff_tim0trg_epwm_trgo;
reg             ff_tim0trg_epwm_oc0 ;
reg             ff_tim0trg_epwm_oc1 ;
reg             ff_tim0trg_epwm_oc2 ;
reg             ff_tim0trg_epwm_oc3 ;
reg             ff_tim0trg_tim0_up  ;
reg             ff_tim0trg_tim1_up  ;
reg             ff_tim0trg_tim2_up  ;
reg             ff_tim0trg_ediag_cmp;
reg             ff_tim1trg_epwm_cmp0;
reg             ff_tim1trg_epwm_cmp1;
reg             ff_tim1trg_epwm_cmp2;
reg             ff_tim1trg_epwm_cmp3;
reg             ff_tim1trg_epwm_cmp4;
reg             ff_tim1trg_epwm_cmp5;
reg             ff_tim1trg_epwm_trgo;
reg             ff_tim1trg_epwm_oc0 ;
reg             ff_tim1trg_epwm_oc1 ;
reg             ff_tim1trg_epwm_oc2 ;
reg             ff_tim1trg_epwm_oc3 ;
reg             ff_tim1trg_tim0_up  ;
reg             ff_tim1trg_tim1_up  ;
reg             ff_tim1trg_tim2_up  ;
reg             ff_tim1trg_ediag_cmp;
reg             ff_tim2trg_epwm_cmp0;
reg             ff_tim2trg_epwm_cmp1;
reg             ff_tim2trg_epwm_cmp2;
reg             ff_tim2trg_epwm_cmp3;
reg             ff_tim2trg_epwm_cmp4;
reg             ff_tim2trg_epwm_cmp5;
reg             ff_tim2trg_epwm_trgo;
reg             ff_tim2trg_epwm_oc0 ;
reg             ff_tim2trg_epwm_oc1 ;
reg             ff_tim2trg_epwm_oc2 ;
reg             ff_tim2trg_epwm_oc3 ;
reg             ff_tim2trg_tim0_up  ;
reg             ff_tim2trg_tim1_up  ;
reg             ff_tim2trg_tim2_up  ;
reg             ff_tim2trg_ediag_cmp;
reg             ff_trgo0_epwm_cmp0  ;
reg             ff_trgo0_epwm_cmp1  ;
reg             ff_trgo0_epwm_cmp2  ;
reg             ff_trgo0_epwm_cmp3  ;
reg             ff_trgo0_epwm_cmp4  ;
reg             ff_trgo0_epwm_cmp5  ;
reg             ff_trgo0_epwm_trgo  ;
reg             ff_trgo0_epwm_oc0   ;
reg             ff_trgo0_epwm_oc1   ;
reg             ff_trgo0_epwm_oc2   ;
reg             ff_trgo0_epwm_oc3   ;
reg             ff_trgo0_tim0_up    ;
reg             ff_trgo0_tim1_up    ;
reg             ff_trgo0_tim2_up    ;
reg             ff_trgo0_ediag_cmp  ;
reg             ff_trgo1_epwm_cmp0  ;
reg             ff_trgo1_epwm_cmp1  ;
reg             ff_trgo1_epwm_cmp2  ;
reg             ff_trgo1_epwm_cmp3  ;
reg             ff_trgo1_epwm_cmp4  ;
reg             ff_trgo1_epwm_cmp5  ;
reg             ff_trgo1_epwm_trgo  ;
reg             ff_trgo1_epwm_oc0   ;
reg             ff_trgo1_epwm_oc1   ;
reg             ff_trgo1_epwm_oc2   ;
reg             ff_trgo1_epwm_oc3   ;
reg             ff_trgo1_tim0_up    ;
reg             ff_trgo1_tim1_up    ;
reg             ff_trgo1_tim2_up    ;
reg             ff_trgo1_ediag_cmp  ;
reg             ff_dbgen_en         ;
reg     [07:0]  ff_dbgen_key        ;
reg             ff_dbglock_lock     ;
reg     [07:0]  ff_dbglock_key      ;
reg     [02:0]  ff_dbgmode_mode     ;
reg             ff_dften_en         ;
reg     [07:0]  ff_dften_key        ;
reg             ff_dftlock_lock     ;
reg     [07:0]  ff_dftlock_key      ;
reg     [03:0]  ff_dftmode_mode     ;

wire    [01:0]  wir_ram0isr_err     ;
wire    [06:0]  wir_ram0synd_synd   ;
wire    [01:0]  wir_ram1isr_err     ;
wire    [06:0]  wir_ram1synd_synd   ;
assign          wir_ram0isr_err     = ram0isr_err[01:0]   ;
assign          wir_ram0synd_synd   = ram0synd_synd[06:0] ;
assign          wir_ram1isr_err     = ram1isr_err[01:0]   ;
assign          wir_ram1synd_synd   = ram1synd_synd[06:0] ;

// ------------------------------------------------------------
// write_process
// ------------------------------------------------------------
wire     wren_chipid         = write_en & (addr[11:2] == 10'h0);
wire     wren_rdp            = write_en & (addr[11:2] == 10'h8);
wire     wren_ram0ier        = write_en & (addr[11:2] == 10'h40);
wire     wren_ram0iclr       = write_en & (addr[11:2] == 10'h42);
wire     wren_ram0injl       = write_en & (addr[11:2] == 10'h45);
wire     wren_ram0injh       = write_en & (addr[11:2] == 10'h46);
wire     wren_ram1ier        = write_en & (addr[11:2] == 10'h4c);
wire     wren_ram1iclr       = write_en & (addr[11:2] == 10'h4e);
wire     wren_ram1injl       = write_en & (addr[11:2] == 10'h51);
wire     wren_ram1injh       = write_en & (addr[11:2] == 10'h52);
wire     wren_adc0trg        = write_en & (addr[11:2] == 10'h80);
wire     wren_adc1trg        = write_en & (addr[11:2] == 10'h81);
wire     wren_tim0trg        = write_en & (addr[11:2] == 10'h82);
wire     wren_tim1trg        = write_en & (addr[11:2] == 10'h83);
wire     wren_tim2trg        = write_en & (addr[11:2] == 10'h84);
wire     wren_trgo0          = write_en & (addr[11:2] == 10'h85);
wire     wren_trgo1          = write_en & (addr[11:2] == 10'h86);
wire     wren_dbgen          = write_en & (addr[11:2] == 10'h380);
wire     wren_dbglock        = write_en & (addr[11:2] == 10'h381);
wire     wren_dbgmode        = write_en & (addr[11:2] == 10'h382);
wire     wren_dften          = write_en & (addr[11:2] == 10'h3c0);
wire     wren_dftlock        = write_en & (addr[11:2] == 10'h3c1);
wire     wren_dftmode        = write_en & (addr[11:2] == 10'h3c2);

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_chipid <= 32'h25240305;
    else if (wren_chipid) begin
        ff_chipid <= wdata[31:0];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_rdp <= 1'h0;
    else if (wren_rdp) begin
        ff_rdp <= wdata[0];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_ram0ier_en <= 1'h0;
    else if (wren_ram0ier) begin
        ff_ram0ier_en <= wdata[0];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_ram0iclr_errclr <= 1'h0;
    else if (wren_ram0iclr)
        ff_ram0iclr_errclr <= wdata[0];
    else 
        ff_ram0iclr_errclr <= 1'h0;
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_ram0injl_injl <= 32'h0;
    else if (wren_ram0injl) begin
        ff_ram0injl_injl <= wdata[31:0];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_ram0injh_injh <= 7'h0;
    else if (wren_ram0injh) begin
        ff_ram0injh_injh <= wdata[6:0];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_ram1ier_en <= 1'h0;
    else if (wren_ram1ier) begin
        ff_ram1ier_en <= wdata[0];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_ram1iclr_errclr <= 1'h0;
    else if (wren_ram1iclr)
        ff_ram1iclr_errclr <= wdata[0];
    else 
        ff_ram1iclr_errclr <= 1'h0;
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_ram1injl_injl <= 32'h0;
    else if (wren_ram1injl) begin
        ff_ram1injl_injl <= wdata[31:0];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_ram1injh_injh <= 7'h0;
    else if (wren_ram1injh) begin
        ff_ram1injh_injh <= wdata[6:0];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc0trg_epwm_cmp0 <= 1'h0;
    else if (wren_adc0trg) begin
        ff_adc0trg_epwm_cmp0 <= wdata[0];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc0trg_epwm_cmp1 <= 1'h0;
    else if (wren_adc0trg) begin
        ff_adc0trg_epwm_cmp1 <= wdata[1];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc0trg_epwm_cmp2 <= 1'h0;
    else if (wren_adc0trg) begin
        ff_adc0trg_epwm_cmp2 <= wdata[2];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc0trg_epwm_cmp3 <= 1'h0;
    else if (wren_adc0trg) begin
        ff_adc0trg_epwm_cmp3 <= wdata[3];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc0trg_epwm_cmp4 <= 1'h0;
    else if (wren_adc0trg) begin
        ff_adc0trg_epwm_cmp4 <= wdata[4];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc0trg_epwm_cmp5 <= 1'h0;
    else if (wren_adc0trg) begin
        ff_adc0trg_epwm_cmp5 <= wdata[5];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc0trg_epwm_trgo <= 1'h0;
    else if (wren_adc0trg) begin
        ff_adc0trg_epwm_trgo <= wdata[6];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc0trg_epwm_oc0 <= 1'h0;
    else if (wren_adc0trg) begin
        ff_adc0trg_epwm_oc0 <= wdata[7];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc0trg_epwm_oc1 <= 1'h0;
    else if (wren_adc0trg) begin
        ff_adc0trg_epwm_oc1 <= wdata[8];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc0trg_epwm_oc2 <= 1'h0;
    else if (wren_adc0trg) begin
        ff_adc0trg_epwm_oc2 <= wdata[9];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc0trg_epwm_oc3 <= 1'h0;
    else if (wren_adc0trg) begin
        ff_adc0trg_epwm_oc3 <= wdata[10];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc0trg_tim0_up <= 1'h0;
    else if (wren_adc0trg) begin
        ff_adc0trg_tim0_up <= wdata[11];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc0trg_tim1_up <= 1'h0;
    else if (wren_adc0trg) begin
        ff_adc0trg_tim1_up <= wdata[12];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc0trg_tim2_up <= 1'h0;
    else if (wren_adc0trg) begin
        ff_adc0trg_tim2_up <= wdata[13];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc0trg_ediag_cmp <= 1'h0;
    else if (wren_adc0trg) begin
        ff_adc0trg_ediag_cmp <= wdata[14];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc1trg_epwm_cmp0 <= 1'h0;
    else if (wren_adc1trg) begin
        ff_adc1trg_epwm_cmp0 <= wdata[0];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc1trg_epwm_cmp1 <= 1'h0;
    else if (wren_adc1trg) begin
        ff_adc1trg_epwm_cmp1 <= wdata[1];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc1trg_epwm_cmp2 <= 1'h0;
    else if (wren_adc1trg) begin
        ff_adc1trg_epwm_cmp2 <= wdata[2];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc1trg_epwm_cmp3 <= 1'h0;
    else if (wren_adc1trg) begin
        ff_adc1trg_epwm_cmp3 <= wdata[3];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc1trg_epwm_cmp4 <= 1'h0;
    else if (wren_adc1trg) begin
        ff_adc1trg_epwm_cmp4 <= wdata[4];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc1trg_epwm_cmp5 <= 1'h0;
    else if (wren_adc1trg) begin
        ff_adc1trg_epwm_cmp5 <= wdata[5];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc1trg_epwm_trgo <= 1'h0;
    else if (wren_adc1trg) begin
        ff_adc1trg_epwm_trgo <= wdata[6];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc1trg_epwm_oc0 <= 1'h0;
    else if (wren_adc1trg) begin
        ff_adc1trg_epwm_oc0 <= wdata[7];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc1trg_epwm_oc1 <= 1'h0;
    else if (wren_adc1trg) begin
        ff_adc1trg_epwm_oc1 <= wdata[8];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc1trg_epwm_oc2 <= 1'h0;
    else if (wren_adc1trg) begin
        ff_adc1trg_epwm_oc2 <= wdata[9];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc1trg_epwm_oc3 <= 1'h0;
    else if (wren_adc1trg) begin
        ff_adc1trg_epwm_oc3 <= wdata[10];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc1trg_tim0_up <= 1'h0;
    else if (wren_adc1trg) begin
        ff_adc1trg_tim0_up <= wdata[11];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc1trg_tim1_up <= 1'h0;
    else if (wren_adc1trg) begin
        ff_adc1trg_tim1_up <= wdata[12];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc1trg_tim2_up <= 1'h0;
    else if (wren_adc1trg) begin
        ff_adc1trg_tim2_up <= wdata[13];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_adc1trg_ediag_cmp <= 1'h0;
    else if (wren_adc1trg) begin
        ff_adc1trg_ediag_cmp <= wdata[14];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim0trg_epwm_cmp0 <= 1'h0;
    else if (wren_tim0trg) begin
        ff_tim0trg_epwm_cmp0 <= wdata[0];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim0trg_epwm_cmp1 <= 1'h0;
    else if (wren_tim0trg) begin
        ff_tim0trg_epwm_cmp1 <= wdata[1];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim0trg_epwm_cmp2 <= 1'h0;
    else if (wren_tim0trg) begin
        ff_tim0trg_epwm_cmp2 <= wdata[2];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim0trg_epwm_cmp3 <= 1'h0;
    else if (wren_tim0trg) begin
        ff_tim0trg_epwm_cmp3 <= wdata[3];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim0trg_epwm_cmp4 <= 1'h0;
    else if (wren_tim0trg) begin
        ff_tim0trg_epwm_cmp4 <= wdata[4];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim0trg_epwm_cmp5 <= 1'h0;
    else if (wren_tim0trg) begin
        ff_tim0trg_epwm_cmp5 <= wdata[5];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim0trg_epwm_trgo <= 1'h0;
    else if (wren_tim0trg) begin
        ff_tim0trg_epwm_trgo <= wdata[6];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim0trg_epwm_oc0 <= 1'h0;
    else if (wren_tim0trg) begin
        ff_tim0trg_epwm_oc0 <= wdata[7];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim0trg_epwm_oc1 <= 1'h0;
    else if (wren_tim0trg) begin
        ff_tim0trg_epwm_oc1 <= wdata[8];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim0trg_epwm_oc2 <= 1'h0;
    else if (wren_tim0trg) begin
        ff_tim0trg_epwm_oc2 <= wdata[9];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim0trg_epwm_oc3 <= 1'h0;
    else if (wren_tim0trg) begin
        ff_tim0trg_epwm_oc3 <= wdata[10];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim0trg_tim0_up <= 1'h0;
    else if (wren_tim0trg) begin
        ff_tim0trg_tim0_up <= wdata[11];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim0trg_tim1_up <= 1'h0;
    else if (wren_tim0trg) begin
        ff_tim0trg_tim1_up <= wdata[12];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim0trg_tim2_up <= 1'h0;
    else if (wren_tim0trg) begin
        ff_tim0trg_tim2_up <= wdata[13];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim0trg_ediag_cmp <= 1'h0;
    else if (wren_tim0trg) begin
        ff_tim0trg_ediag_cmp <= wdata[14];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim1trg_epwm_cmp0 <= 1'h0;
    else if (wren_tim1trg) begin
        ff_tim1trg_epwm_cmp0 <= wdata[0];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim1trg_epwm_cmp1 <= 1'h0;
    else if (wren_tim1trg) begin
        ff_tim1trg_epwm_cmp1 <= wdata[1];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim1trg_epwm_cmp2 <= 1'h0;
    else if (wren_tim1trg) begin
        ff_tim1trg_epwm_cmp2 <= wdata[2];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim1trg_epwm_cmp3 <= 1'h0;
    else if (wren_tim1trg) begin
        ff_tim1trg_epwm_cmp3 <= wdata[3];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim1trg_epwm_cmp4 <= 1'h0;
    else if (wren_tim1trg) begin
        ff_tim1trg_epwm_cmp4 <= wdata[4];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim1trg_epwm_cmp5 <= 1'h0;
    else if (wren_tim1trg) begin
        ff_tim1trg_epwm_cmp5 <= wdata[5];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim1trg_epwm_trgo <= 1'h0;
    else if (wren_tim1trg) begin
        ff_tim1trg_epwm_trgo <= wdata[6];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim1trg_epwm_oc0 <= 1'h0;
    else if (wren_tim1trg) begin
        ff_tim1trg_epwm_oc0 <= wdata[7];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim1trg_epwm_oc1 <= 1'h0;
    else if (wren_tim1trg) begin
        ff_tim1trg_epwm_oc1 <= wdata[8];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim1trg_epwm_oc2 <= 1'h0;
    else if (wren_tim1trg) begin
        ff_tim1trg_epwm_oc2 <= wdata[9];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim1trg_epwm_oc3 <= 1'h0;
    else if (wren_tim1trg) begin
        ff_tim1trg_epwm_oc3 <= wdata[10];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim1trg_tim0_up <= 1'h0;
    else if (wren_tim1trg) begin
        ff_tim1trg_tim0_up <= wdata[11];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim1trg_tim1_up <= 1'h0;
    else if (wren_tim1trg) begin
        ff_tim1trg_tim1_up <= wdata[12];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim1trg_tim2_up <= 1'h0;
    else if (wren_tim1trg) begin
        ff_tim1trg_tim2_up <= wdata[13];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim1trg_ediag_cmp <= 1'h0;
    else if (wren_tim1trg) begin
        ff_tim1trg_ediag_cmp <= wdata[14];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim2trg_epwm_cmp0 <= 1'h0;
    else if (wren_tim2trg) begin
        ff_tim2trg_epwm_cmp0 <= wdata[0];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim2trg_epwm_cmp1 <= 1'h0;
    else if (wren_tim2trg) begin
        ff_tim2trg_epwm_cmp1 <= wdata[1];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim2trg_epwm_cmp2 <= 1'h0;
    else if (wren_tim2trg) begin
        ff_tim2trg_epwm_cmp2 <= wdata[2];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim2trg_epwm_cmp3 <= 1'h0;
    else if (wren_tim2trg) begin
        ff_tim2trg_epwm_cmp3 <= wdata[3];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim2trg_epwm_cmp4 <= 1'h0;
    else if (wren_tim2trg) begin
        ff_tim2trg_epwm_cmp4 <= wdata[4];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim2trg_epwm_cmp5 <= 1'h0;
    else if (wren_tim2trg) begin
        ff_tim2trg_epwm_cmp5 <= wdata[5];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim2trg_epwm_trgo <= 1'h0;
    else if (wren_tim2trg) begin
        ff_tim2trg_epwm_trgo <= wdata[6];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim2trg_epwm_oc0 <= 1'h0;
    else if (wren_tim2trg) begin
        ff_tim2trg_epwm_oc0 <= wdata[7];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim2trg_epwm_oc1 <= 1'h0;
    else if (wren_tim2trg) begin
        ff_tim2trg_epwm_oc1 <= wdata[8];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim2trg_epwm_oc2 <= 1'h0;
    else if (wren_tim2trg) begin
        ff_tim2trg_epwm_oc2 <= wdata[9];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim2trg_epwm_oc3 <= 1'h0;
    else if (wren_tim2trg) begin
        ff_tim2trg_epwm_oc3 <= wdata[10];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim2trg_tim0_up <= 1'h0;
    else if (wren_tim2trg) begin
        ff_tim2trg_tim0_up <= wdata[11];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim2trg_tim1_up <= 1'h0;
    else if (wren_tim2trg) begin
        ff_tim2trg_tim1_up <= wdata[12];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim2trg_tim2_up <= 1'h0;
    else if (wren_tim2trg) begin
        ff_tim2trg_tim2_up <= wdata[13];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_tim2trg_ediag_cmp <= 1'h0;
    else if (wren_tim2trg) begin
        ff_tim2trg_ediag_cmp <= wdata[14];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo0_epwm_cmp0 <= 1'h0;
    else if (wren_trgo0) begin
        ff_trgo0_epwm_cmp0 <= wdata[0];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo0_epwm_cmp1 <= 1'h0;
    else if (wren_trgo0) begin
        ff_trgo0_epwm_cmp1 <= wdata[1];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo0_epwm_cmp2 <= 1'h0;
    else if (wren_trgo0) begin
        ff_trgo0_epwm_cmp2 <= wdata[2];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo0_epwm_cmp3 <= 1'h0;
    else if (wren_trgo0) begin
        ff_trgo0_epwm_cmp3 <= wdata[3];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo0_epwm_cmp4 <= 1'h0;
    else if (wren_trgo0) begin
        ff_trgo0_epwm_cmp4 <= wdata[4];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo0_epwm_cmp5 <= 1'h0;
    else if (wren_trgo0) begin
        ff_trgo0_epwm_cmp5 <= wdata[5];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo0_epwm_trgo <= 1'h0;
    else if (wren_trgo0) begin
        ff_trgo0_epwm_trgo <= wdata[6];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo0_epwm_oc0 <= 1'h0;
    else if (wren_trgo0) begin
        ff_trgo0_epwm_oc0 <= wdata[7];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo0_epwm_oc1 <= 1'h0;
    else if (wren_trgo0) begin
        ff_trgo0_epwm_oc1 <= wdata[8];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo0_epwm_oc2 <= 1'h0;
    else if (wren_trgo0) begin
        ff_trgo0_epwm_oc2 <= wdata[9];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo0_epwm_oc3 <= 1'h0;
    else if (wren_trgo0) begin
        ff_trgo0_epwm_oc3 <= wdata[10];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo0_tim0_up <= 1'h0;
    else if (wren_trgo0) begin
        ff_trgo0_tim0_up <= wdata[11];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo0_tim1_up <= 1'h0;
    else if (wren_trgo0) begin
        ff_trgo0_tim1_up <= wdata[12];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo0_tim2_up <= 1'h0;
    else if (wren_trgo0) begin
        ff_trgo0_tim2_up <= wdata[13];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo0_ediag_cmp <= 1'h0;
    else if (wren_trgo0) begin
        ff_trgo0_ediag_cmp <= wdata[14];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo1_epwm_cmp0 <= 1'h0;
    else if (wren_trgo1) begin
        ff_trgo1_epwm_cmp0 <= wdata[0];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo1_epwm_cmp1 <= 1'h0;
    else if (wren_trgo1) begin
        ff_trgo1_epwm_cmp1 <= wdata[1];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo1_epwm_cmp2 <= 1'h0;
    else if (wren_trgo1) begin
        ff_trgo1_epwm_cmp2 <= wdata[2];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo1_epwm_cmp3 <= 1'h0;
    else if (wren_trgo1) begin
        ff_trgo1_epwm_cmp3 <= wdata[3];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo1_epwm_cmp4 <= 1'h0;
    else if (wren_trgo1) begin
        ff_trgo1_epwm_cmp4 <= wdata[4];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo1_epwm_cmp5 <= 1'h0;
    else if (wren_trgo1) begin
        ff_trgo1_epwm_cmp5 <= wdata[5];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo1_epwm_trgo <= 1'h0;
    else if (wren_trgo1) begin
        ff_trgo1_epwm_trgo <= wdata[6];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo1_epwm_oc0 <= 1'h0;
    else if (wren_trgo1) begin
        ff_trgo1_epwm_oc0 <= wdata[7];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo1_epwm_oc1 <= 1'h0;
    else if (wren_trgo1) begin
        ff_trgo1_epwm_oc1 <= wdata[8];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo1_epwm_oc2 <= 1'h0;
    else if (wren_trgo1) begin
        ff_trgo1_epwm_oc2 <= wdata[9];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo1_epwm_oc3 <= 1'h0;
    else if (wren_trgo1) begin
        ff_trgo1_epwm_oc3 <= wdata[10];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo1_tim0_up <= 1'h0;
    else if (wren_trgo1) begin
        ff_trgo1_tim0_up <= wdata[11];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo1_tim1_up <= 1'h0;
    else if (wren_trgo1) begin
        ff_trgo1_tim1_up <= wdata[12];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo1_tim2_up <= 1'h0;
    else if (wren_trgo1) begin
        ff_trgo1_tim2_up <= wdata[13];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_trgo1_ediag_cmp <= 1'h0;
    else if (wren_trgo1) begin
        ff_trgo1_ediag_cmp <= wdata[14];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_dbgen_en <= 1'h0;
    else if (wren_dbgen) begin
        ff_dbgen_en <= wdata[0];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_dbgen_key <= 8'h0;
    else if (wren_dbgen) begin
        ff_dbgen_key <= wdata[31:24];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_dbglock_lock <= 1'h0;
    else if (wren_dbglock) begin
        ff_dbglock_lock <= wdata[0];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_dbglock_key <= 8'h0;
    else if (wren_dbglock) begin
        ff_dbglock_key <= wdata[31:24];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_dbgmode_mode <= 3'h0;
    else if (wren_dbgmode) begin
        ff_dbgmode_mode <= wdata[2:0];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_dften_en <= 1'h0;
    else if (wren_dften) begin
        ff_dften_en <= wdata[0];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_dften_key <= 8'h0;
    else if (wren_dften) begin
        ff_dften_key <= wdata[31:24];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_dftlock_lock <= 1'h0;
    else if (wren_dftlock) begin
        ff_dftlock_lock <= wdata[0];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_dftlock_key <= 8'h0;
    else if (wren_dftlock) begin
        ff_dftlock_key <= wdata[31:24];
    end
end

always @(posedge hclk or negedge hrstn) begin
    if (!hrstn)
        ff_dftmode_mode <= 4'h0;
    else if (wren_dftmode) begin
        ff_dftmode_mode <= wdata[3:0];
    end
end


// ------------------------------------------------------------
// read_process
// ------------------------------------------------------------

wire  [31:0]  wir_r_chipid   = {ff_chipid[31:0]};
wire  [31:0]  wir_r_rdp      = {31'h0, ff_rdp};
wire  [31:0]  wir_r_ram0ier  = {31'h0, ff_ram0ier_en};
wire  [31:0]  wir_r_ram0isr  = {30'h0, wir_ram0isr_err[1:0]};
wire  [31:0]  wir_r_ram0synd = {25'h0, wir_ram0synd_synd[6:0]};
wire  [31:0]  wir_r_ram0injl = {ff_ram0injl_injl[31:0]};
wire  [31:0]  wir_r_ram0injh = {25'h0, ff_ram0injh_injh[6:0]};
wire  [31:0]  wir_r_ram1ier  = {31'h0, ff_ram1ier_en};
wire  [31:0]  wir_r_ram1isr  = {30'h0, wir_ram1isr_err[1:0]};
wire  [31:0]  wir_r_ram1synd = {25'h0, wir_ram1synd_synd[6:0]};
wire  [31:0]  wir_r_ram1injl = {ff_ram1injl_injl[31:0]};
wire  [31:0]  wir_r_ram1injh = {25'h0, ff_ram1injh_injh[6:0]};
wire  [31:0]  wir_r_adc0trg  = {17'h0, ff_adc0trg_ediag_cmp, ff_adc0trg_tim2_up, ff_adc0trg_tim1_up, ff_adc0trg_tim0_up, ff_adc0trg_epwm_oc3, ff_adc0trg_epwm_oc2, ff_adc0trg_epwm_oc1, ff_adc0trg_epwm_oc0, ff_adc0trg_epwm_trgo, ff_adc0trg_epwm_cmp5, ff_adc0trg_epwm_cmp4, ff_adc0trg_epwm_cmp3, ff_adc0trg_epwm_cmp2, ff_adc0trg_epwm_cmp1, ff_adc0trg_epwm_cmp0};
wire  [31:0]  wir_r_adc1trg  = {17'h0, ff_adc1trg_ediag_cmp, ff_adc1trg_tim2_up, ff_adc1trg_tim1_up, ff_adc1trg_tim0_up, ff_adc1trg_epwm_oc3, ff_adc1trg_epwm_oc2, ff_adc1trg_epwm_oc1, ff_adc1trg_epwm_oc0, ff_adc1trg_epwm_trgo, ff_adc1trg_epwm_cmp5, ff_adc1trg_epwm_cmp4, ff_adc1trg_epwm_cmp3, ff_adc1trg_epwm_cmp2, ff_adc1trg_epwm_cmp1, ff_adc1trg_epwm_cmp0};
wire  [31:0]  wir_r_tim0trg  = {17'h0, ff_tim0trg_ediag_cmp, ff_tim0trg_tim2_up, ff_tim0trg_tim1_up, ff_tim0trg_tim0_up, ff_tim0trg_epwm_oc3, ff_tim0trg_epwm_oc2, ff_tim0trg_epwm_oc1, ff_tim0trg_epwm_oc0, ff_tim0trg_epwm_trgo, ff_tim0trg_epwm_cmp5, ff_tim0trg_epwm_cmp4, ff_tim0trg_epwm_cmp3, ff_tim0trg_epwm_cmp2, ff_tim0trg_epwm_cmp1, ff_tim0trg_epwm_cmp0};
wire  [31:0]  wir_r_tim1trg  = {17'h0, ff_tim1trg_ediag_cmp, ff_tim1trg_tim2_up, ff_tim1trg_tim1_up, ff_tim1trg_tim0_up, ff_tim1trg_epwm_oc3, ff_tim1trg_epwm_oc2, ff_tim1trg_epwm_oc1, ff_tim1trg_epwm_oc0, ff_tim1trg_epwm_trgo, ff_tim1trg_epwm_cmp5, ff_tim1trg_epwm_cmp4, ff_tim1trg_epwm_cmp3, ff_tim1trg_epwm_cmp2, ff_tim1trg_epwm_cmp1, ff_tim1trg_epwm_cmp0};
wire  [31:0]  wir_r_tim2trg  = {17'h0, ff_tim2trg_ediag_cmp, ff_tim2trg_tim2_up, ff_tim2trg_tim1_up, ff_tim2trg_tim0_up, ff_tim2trg_epwm_oc3, ff_tim2trg_epwm_oc2, ff_tim2trg_epwm_oc1, ff_tim2trg_epwm_oc0, ff_tim2trg_epwm_trgo, ff_tim2trg_epwm_cmp5, ff_tim2trg_epwm_cmp4, ff_tim2trg_epwm_cmp3, ff_tim2trg_epwm_cmp2, ff_tim2trg_epwm_cmp1, ff_tim2trg_epwm_cmp0};
wire  [31:0]  wir_r_trgo0    = {17'h0, ff_trgo0_ediag_cmp, ff_trgo0_tim2_up, ff_trgo0_tim1_up, ff_trgo0_tim0_up, ff_trgo0_epwm_oc3, ff_trgo0_epwm_oc2, ff_trgo0_epwm_oc1, ff_trgo0_epwm_oc0, ff_trgo0_epwm_trgo, ff_trgo0_epwm_cmp5, ff_trgo0_epwm_cmp4, ff_trgo0_epwm_cmp3, ff_trgo0_epwm_cmp2, ff_trgo0_epwm_cmp1, ff_trgo0_epwm_cmp0};
wire  [31:0]  wir_r_trgo1    = {17'h0, ff_trgo1_ediag_cmp, ff_trgo1_tim2_up, ff_trgo1_tim1_up, ff_trgo1_tim0_up, ff_trgo1_epwm_oc3, ff_trgo1_epwm_oc2, ff_trgo1_epwm_oc1, ff_trgo1_epwm_oc0, ff_trgo1_epwm_trgo, ff_trgo1_epwm_cmp5, ff_trgo1_epwm_cmp4, ff_trgo1_epwm_cmp3, ff_trgo1_epwm_cmp2, ff_trgo1_epwm_cmp1, ff_trgo1_epwm_cmp0};
wire  [31:0]  wir_r_dbgen    = {ff_dbgen_key[31:24], 23'h0, ff_dbgen_en};
wire  [31:0]  wir_r_dbglock  = {ff_dbglock_key[31:24], 23'h0, ff_dbglock_lock};
wire  [31:0]  wir_r_dbgmode  = {29'h0, ff_dbgmode_mode[2:0]};
wire  [31:0]  wir_r_dften    = {ff_dften_key[31:24], 23'h0, ff_dften_en};
wire  [31:0]  wir_r_dftlock  = {ff_dftlock_key[31:24], 23'h0, ff_dftlock_lock};
wire  [31:0]  wir_r_dftmode  = {28'h0, ff_dftmode_mode[3:0]};

always @ (*) begin
    ff_rdata = 32'h0;
    if (read_en) begin
        case (addr[11:2])
            10'b0000000000     :    ff_rdata = wir_r_chipid;
            10'b0000001000     :    ff_rdata = wir_r_rdp;
            10'b0001000000     :    ff_rdata = wir_r_ram0ier;
            10'b0001000001     :    ff_rdata = wir_r_ram0isr;
            10'b0001000100     :    ff_rdata = wir_r_ram0synd;
            10'b0001000101     :    ff_rdata = wir_r_ram0injl;
            10'b0001000110     :    ff_rdata = wir_r_ram0injh;
            10'b0001001100     :    ff_rdata = wir_r_ram1ier;
            10'b0001001101     :    ff_rdata = wir_r_ram1isr;
            10'b0001010000     :    ff_rdata = wir_r_ram1synd;
            10'b0001010001     :    ff_rdata = wir_r_ram1injl;
            10'b0001010010     :    ff_rdata = wir_r_ram1injh;
            10'b0010000000     :    ff_rdata = wir_r_adc0trg;
            10'b0010000001     :    ff_rdata = wir_r_adc1trg;
            10'b0010000010     :    ff_rdata = wir_r_tim0trg;
            10'b0010000011     :    ff_rdata = wir_r_tim1trg;
            10'b0010000100     :    ff_rdata = wir_r_tim2trg;
            10'b0010000101     :    ff_rdata = wir_r_trgo0;
            10'b0010000110     :    ff_rdata = wir_r_trgo1;
            10'b1110000000     :    ff_rdata = wir_r_dbgen;
            10'b1110000001     :    ff_rdata = wir_r_dbglock;
            10'b1110000010     :    ff_rdata = wir_r_dbgmode;
            10'b1111000000     :    ff_rdata = wir_r_dften;
            10'b1111000001     :    ff_rdata = wir_r_dftlock;
            10'b1111000010     :    ff_rdata = wir_r_dftmode;
            default: ff_rdata = 32'h0;
        endcase
    end
end
// ------------------------------------------------------------
// Assign
// ------------------------------------------------------------
assign  chipid              = ff_chipid           ;
assign  rdp                 = ff_rdp              ;
assign  ram0ier_en          = ff_ram0ier_en       ;
assign  ram0iclr_errclr     = ff_ram0iclr_errclr  ;
assign  ram0injl_injl       = ff_ram0injl_injl    ;
assign  ram0injh_injh       = ff_ram0injh_injh    ;
assign  ram1ier_en          = ff_ram1ier_en       ;
assign  ram1iclr_errclr     = ff_ram1iclr_errclr  ;
assign  ram1injl_injl       = ff_ram1injl_injl    ;
assign  ram1injh_injh       = ff_ram1injh_injh    ;
assign  adc0trg_epwm_cmp0   = ff_adc0trg_epwm_cmp0;
assign  adc0trg_epwm_cmp1   = ff_adc0trg_epwm_cmp1;
assign  adc0trg_epwm_cmp2   = ff_adc0trg_epwm_cmp2;
assign  adc0trg_epwm_cmp3   = ff_adc0trg_epwm_cmp3;
assign  adc0trg_epwm_cmp4   = ff_adc0trg_epwm_cmp4;
assign  adc0trg_epwm_cmp5   = ff_adc0trg_epwm_cmp5;
assign  adc0trg_epwm_trgo   = ff_adc0trg_epwm_trgo;
assign  adc0trg_epwm_oc0    = ff_adc0trg_epwm_oc0 ;
assign  adc0trg_epwm_oc1    = ff_adc0trg_epwm_oc1 ;
assign  adc0trg_epwm_oc2    = ff_adc0trg_epwm_oc2 ;
assign  adc0trg_epwm_oc3    = ff_adc0trg_epwm_oc3 ;
assign  adc0trg_tim0_up     = ff_adc0trg_tim0_up  ;
assign  adc0trg_tim1_up     = ff_adc0trg_tim1_up  ;
assign  adc0trg_tim2_up     = ff_adc0trg_tim2_up  ;
assign  adc0trg_ediag_cmp   = ff_adc0trg_ediag_cmp;
assign  adc1trg_epwm_cmp0   = ff_adc1trg_epwm_cmp0;
assign  adc1trg_epwm_cmp1   = ff_adc1trg_epwm_cmp1;
assign  adc1trg_epwm_cmp2   = ff_adc1trg_epwm_cmp2;
assign  adc1trg_epwm_cmp3   = ff_adc1trg_epwm_cmp3;
assign  adc1trg_epwm_cmp4   = ff_adc1trg_epwm_cmp4;
assign  adc1trg_epwm_cmp5   = ff_adc1trg_epwm_cmp5;
assign  adc1trg_epwm_trgo   = ff_adc1trg_epwm_trgo;
assign  adc1trg_epwm_oc0    = ff_adc1trg_epwm_oc0 ;
assign  adc1trg_epwm_oc1    = ff_adc1trg_epwm_oc1 ;
assign  adc1trg_epwm_oc2    = ff_adc1trg_epwm_oc2 ;
assign  adc1trg_epwm_oc3    = ff_adc1trg_epwm_oc3 ;
assign  adc1trg_tim0_up     = ff_adc1trg_tim0_up  ;
assign  adc1trg_tim1_up     = ff_adc1trg_tim1_up  ;
assign  adc1trg_tim2_up     = ff_adc1trg_tim2_up  ;
assign  adc1trg_ediag_cmp   = ff_adc1trg_ediag_cmp;
assign  tim0trg_epwm_cmp0   = ff_tim0trg_epwm_cmp0;
assign  tim0trg_epwm_cmp1   = ff_tim0trg_epwm_cmp1;
assign  tim0trg_epwm_cmp2   = ff_tim0trg_epwm_cmp2;
assign  tim0trg_epwm_cmp3   = ff_tim0trg_epwm_cmp3;
assign  tim0trg_epwm_cmp4   = ff_tim0trg_epwm_cmp4;
assign  tim0trg_epwm_cmp5   = ff_tim0trg_epwm_cmp5;
assign  tim0trg_epwm_trgo   = ff_tim0trg_epwm_trgo;
assign  tim0trg_epwm_oc0    = ff_tim0trg_epwm_oc0 ;
assign  tim0trg_epwm_oc1    = ff_tim0trg_epwm_oc1 ;
assign  tim0trg_epwm_oc2    = ff_tim0trg_epwm_oc2 ;
assign  tim0trg_epwm_oc3    = ff_tim0trg_epwm_oc3 ;
assign  tim0trg_tim0_up     = ff_tim0trg_tim0_up  ;
assign  tim0trg_tim1_up     = ff_tim0trg_tim1_up  ;
assign  tim0trg_tim2_up     = ff_tim0trg_tim2_up  ;
assign  tim0trg_ediag_cmp   = ff_tim0trg_ediag_cmp;
assign  tim1trg_epwm_cmp0   = ff_tim1trg_epwm_cmp0;
assign  tim1trg_epwm_cmp1   = ff_tim1trg_epwm_cmp1;
assign  tim1trg_epwm_cmp2   = ff_tim1trg_epwm_cmp2;
assign  tim1trg_epwm_cmp3   = ff_tim1trg_epwm_cmp3;
assign  tim1trg_epwm_cmp4   = ff_tim1trg_epwm_cmp4;
assign  tim1trg_epwm_cmp5   = ff_tim1trg_epwm_cmp5;
assign  tim1trg_epwm_trgo   = ff_tim1trg_epwm_trgo;
assign  tim1trg_epwm_oc0    = ff_tim1trg_epwm_oc0 ;
assign  tim1trg_epwm_oc1    = ff_tim1trg_epwm_oc1 ;
assign  tim1trg_epwm_oc2    = ff_tim1trg_epwm_oc2 ;
assign  tim1trg_epwm_oc3    = ff_tim1trg_epwm_oc3 ;
assign  tim1trg_tim0_up     = ff_tim1trg_tim0_up  ;
assign  tim1trg_tim1_up     = ff_tim1trg_tim1_up  ;
assign  tim1trg_tim2_up     = ff_tim1trg_tim2_up  ;
assign  tim1trg_ediag_cmp   = ff_tim1trg_ediag_cmp;
assign  tim2trg_epwm_cmp0   = ff_tim2trg_epwm_cmp0;
assign  tim2trg_epwm_cmp1   = ff_tim2trg_epwm_cmp1;
assign  tim2trg_epwm_cmp2   = ff_tim2trg_epwm_cmp2;
assign  tim2trg_epwm_cmp3   = ff_tim2trg_epwm_cmp3;
assign  tim2trg_epwm_cmp4   = ff_tim2trg_epwm_cmp4;
assign  tim2trg_epwm_cmp5   = ff_tim2trg_epwm_cmp5;
assign  tim2trg_epwm_trgo   = ff_tim2trg_epwm_trgo;
assign  tim2trg_epwm_oc0    = ff_tim2trg_epwm_oc0 ;
assign  tim2trg_epwm_oc1    = ff_tim2trg_epwm_oc1 ;
assign  tim2trg_epwm_oc2    = ff_tim2trg_epwm_oc2 ;
assign  tim2trg_epwm_oc3    = ff_tim2trg_epwm_oc3 ;
assign  tim2trg_tim0_up     = ff_tim2trg_tim0_up  ;
assign  tim2trg_tim1_up     = ff_tim2trg_tim1_up  ;
assign  tim2trg_tim2_up     = ff_tim2trg_tim2_up  ;
assign  tim2trg_ediag_cmp   = ff_tim2trg_ediag_cmp;
assign  trgo0_epwm_cmp0     = ff_trgo0_epwm_cmp0  ;
assign  trgo0_epwm_cmp1     = ff_trgo0_epwm_cmp1  ;
assign  trgo0_epwm_cmp2     = ff_trgo0_epwm_cmp2  ;
assign  trgo0_epwm_cmp3     = ff_trgo0_epwm_cmp3  ;
assign  trgo0_epwm_cmp4     = ff_trgo0_epwm_cmp4  ;
assign  trgo0_epwm_cmp5     = ff_trgo0_epwm_cmp5  ;
assign  trgo0_epwm_trgo     = ff_trgo0_epwm_trgo  ;
assign  trgo0_epwm_oc0      = ff_trgo0_epwm_oc0   ;
assign  trgo0_epwm_oc1      = ff_trgo0_epwm_oc1   ;
assign  trgo0_epwm_oc2      = ff_trgo0_epwm_oc2   ;
assign  trgo0_epwm_oc3      = ff_trgo0_epwm_oc3   ;
assign  trgo0_tim0_up       = ff_trgo0_tim0_up    ;
assign  trgo0_tim1_up       = ff_trgo0_tim1_up    ;
assign  trgo0_tim2_up       = ff_trgo0_tim2_up    ;
assign  trgo0_ediag_cmp     = ff_trgo0_ediag_cmp  ;
assign  trgo1_epwm_cmp0     = ff_trgo1_epwm_cmp0  ;
assign  trgo1_epwm_cmp1     = ff_trgo1_epwm_cmp1  ;
assign  trgo1_epwm_cmp2     = ff_trgo1_epwm_cmp2  ;
assign  trgo1_epwm_cmp3     = ff_trgo1_epwm_cmp3  ;
assign  trgo1_epwm_cmp4     = ff_trgo1_epwm_cmp4  ;
assign  trgo1_epwm_cmp5     = ff_trgo1_epwm_cmp5  ;
assign  trgo1_epwm_trgo     = ff_trgo1_epwm_trgo  ;
assign  trgo1_epwm_oc0      = ff_trgo1_epwm_oc0   ;
assign  trgo1_epwm_oc1      = ff_trgo1_epwm_oc1   ;
assign  trgo1_epwm_oc2      = ff_trgo1_epwm_oc2   ;
assign  trgo1_epwm_oc3      = ff_trgo1_epwm_oc3   ;
assign  trgo1_tim0_up       = ff_trgo1_tim0_up    ;
assign  trgo1_tim1_up       = ff_trgo1_tim1_up    ;
assign  trgo1_tim2_up       = ff_trgo1_tim2_up    ;
assign  trgo1_ediag_cmp     = ff_trgo1_ediag_cmp  ;
assign  dbgen_en            = ff_dbgen_en         ;
assign  dbgen_key           = ff_dbgen_key        ;
assign  dbglock_lock        = ff_dbglock_lock     ;
assign  dbglock_key         = ff_dbglock_key      ;
assign  dbgmode_mode        = ff_dbgmode_mode     ;
assign  dften_en            = ff_dften_en         ;
assign  dften_key           = ff_dften_key        ;
assign  dftlock_lock        = ff_dftlock_lock     ;
assign  dftlock_key         = ff_dftlock_key      ;
assign  dftmode_mode        = ff_dftmode_mode     ;
// ------------------------------------------------------------
// End of the module
// ------------------------------------------------------------
endmodule
